A variable frequency oscillator (VFO) generally produces an oscillating signal with a frequency that may be controlled by an external control. The control signal may generally comprise a variable voltage (for a voltage controlled oscillator [VCO]), a variable current, or a numeric digital value (for a digital or numerically controlled oscillator [NCO]). VFOs generally have characteristic gain curves such as those shown in FIG. 1. This gain curve relates the frequency of oscillation to the input control amplitude. FIG. 1 shows gain curves for a hypothetical oscillator over three different manufacturing process runs. For CMOS processes, manufacturing variations occur in a wide variety of parameters but the most important, from the viewpoint of circuit operation, are transistor threshold, transconductance, and parasitic capacitance. The three curves of FIG. 1 represent fast, typical and slow process versions of the same oscillator design. A slow process corner (e.g., a process resulting in a VFO with gain curve 101) may have high threshold transistors of low transconductance (gm) and high parasitic capacitance. Gain curve 102 represents a nominal center of the manufacturing process. A fast process corner (e.g., a process resulting in a VFO with gain curve 103) may have transistors of low threshold, high gm, and low parasitic capacitance.
FIG. 1 shows that an oscillator may have unacceptable frequency output characteristics under some process variations. Frequency 110 represents the target frequency for a hypothetical application of an oscillator. FIG. 1 shows that an oscillator with slow gain curve 101 cannot attain nominal center frequency 110, because no point on slow gain curve 101 intersects the target frequency. Thus, for this hypothetical application, chips manufactured at a slow process corner generally cannot be used.
FIG. 2 shows a more desirable set of gain curves (101′, 102′, 103′) for a hypothetical oscillator which is usable under all manufacturing process variations. In such a hypothetical oscillator, nominal center frequency 110′ may be similar for all 3 curves, such that only the slope (gain) changes. Generally when such an oscillator is used in a phase locked loop, the lowest jitter and highest stability may be obtained with the minimum gain slope for the application.
Similar curves can be generated for voltage and temperature variations. Variations in voltage generally change the magnitude of the range control signal as well as the gain slope. Temperature variations generally change both the slope and center frequency. While process variations are generally constant for a given chip, voltage and temperature variations may change over time. Therefore, it is desirable to produce a variable frequency oscillator which can compensate for process, voltage, and temperature (PVT) variations.
The problem of process and voltage variation particularly applies to ring oscillators. VFOs which contain tuned resonators (e.g., inductors, crystals, SAW resonators, etc.) generally do not vary as much in frequency over voltage and process variations. Temperature compensation for such oscillators is generally handled using circuitry specific to the type of resonator.
Many conventional ring oscillators use an internal current to control the frequency of oscillation. Stages of these oscillators may include current starved inverters or current switch buffers. Conventional approaches to compensating for process and operational variations in such ring oscillators typically use analog techniques.
For example, one conventional approach achieves the process compensation by using an analog measurement system which determines the channel strength of the P and N type transistors to generate a current inversely proportional thereto. An additional measurement circuit measures the trip or switching voltage level between the P and N transistors of a dummy ring oscillator stage. The two measurements may be combined to modify the current generated by the control voltage to control the frequency. This method generally does not measure the capacitance variation of the oscillator stages and so may not achieve full compensation for process variations.
Another conventional approach uses an analog means which subtracts a current from an accurate current reference (which is relatively independent of PVT variations) from a tracking current, which generates a difference current having both process-dependent and process-independent current components. This difference current may be generally proportional to the PVT variation and may be used to attenuate the effect of the oscillator control voltage in a manner which lessens the effects of the PVT variation. This method generally requires two analog current references: the process independent reference and the tracking reference. Such analog circuitry, however, generally occupies a relatively large silicon area using conventional CMOS processes.
Yet another conventional approach achieves the desired low gain in the presence of PVT variations by selecting from among a plurality of ring oscillators which oscillate at different frequencies. The oscillator forms part of a PLL system, and the lock/unlock state of the PLL may be used to determine which oscillator is within the correct frequency and gain range.
It can be seen that circuits and methods for compensating the gain and center frequency of a variable oscillator (and particularly a ring oscillator) for variations due to process, voltage, and temperature is desirable. In addition, a digital circuit is preferable to analog for modern CMOS processes where digital logic tends to occupy less die area than analog functions. Furthermore, a reduction in slope of the gain curve (e.g., reduced variation in frequency for equal variation in control signal) is desirable when the variable oscillator is used in phase locked loop applications. The compensation circuits and methods should allow such a reduction in slope while preserving the usability of the variable oscillator for a wide range of PVT variations.